This invention relates generally to latch-up protection circuitry for integrated circuits using complementary MOS circuit technology and, in particular, to latch-up protection circuitry which largely voids occurrence of latch-up effects.
In general, integrated circuits which use complementary MOS technology have a semiconductor substrate which does not lie at the ground potential of the integrated circuit, but is negatively charged by a substrate bias generator. It is known that biasing a semiconductor substrate reduces the transistor and junction capacitances and improves the switching speed of the integrated circuit. For example, for a semiconductor substrate of p-conductive material having inserted therein n-conductive, well-shaped semiconductor zones, the substrate is typically negatively biased in the range -2 to -3 volts. The source regions of field effect transistors that are provided on the semiconductor substrate and which are outside of the wellshaped semiconductor zone are connected to a ground potential, since the semiconductor substrate has a negative bias.
When a positive supply voltage for the integrated circuit is switched on, the p-conductive semiconductor substrate is initially "floating", that is, it is not connected to an external potentials.
This floating condition terminates when the substrate bias generator takes effect. The time span between the turn on of the positive supply voltage and the activation of the substrate bias generator is essentially influenced by such factors as clock frequency, existing coupling capacitances and existing capacitive load. During the time of "floating", the semiconductor substrate can be temporarily charged to a positive bias via the junction capacitances which are present, first, between the well-shaped semiconductor zone and the substrate and, second, between the substrate and the source regions of the field effect transistors which are connected to ground potential. This initial positive bias is not removed until the substrate bias generator takes effect, that is, until the negative substrate bias gradually builds up at the output of the substrate bias generator. Even during operation of the integrated circuit, high currents that are shunted by the semiconductor substrate via the substrate bias generator to a terminal of the substrate lying at ground potential can lead to a positive bias of the semiconductor substrate. This is due to a voltage drop at the internal resistance of the substrate bias generator. Positive biases, however, represent a high safety risk for the integrated circuit since a latch-up effect can be triggered thereby disabling the integrated circuit.
For a better understanding of the latch-up effect, it can be assumed that four successive semiconductor layers of alternating conductivity types are generally present between a terminal of a field effect transistor of a first channel type lying in the well-shaped semiconductor zone and a terminal of a field effect transistor of a second channel type located outside of this zone on the semiconductor substrate. The terminal of the former transistor forms the first semiconductor layer, the wellshaped semiconductor zone forms the second, the semiconductor substrate forms the third, and the terminal of the latter transistor forms the fourth semiconductor layer. As a consequence of this structure, a parasitic bipolar pnp transistor and an npn transistor are created. The collector of the pnp transistor corresponds to the base of the npn transistor, and the base of the pnp transistor corresponds to the collector of the npn transistor. This structure forms a four layer pnpn diode, as is typically found in a thyristor. When the semiconductor substrate has a positive bias, the pn junction between the third and fourth semiconductor layers can be biased such that a current flow occurs between the latter transistor terminals, this current path to be attributed to a parasitic thyristor effect within the four layer structure. The current path then continues to exist even after the positive bias is removed from the substrate and this current path can thermally overload the integrated circuit.
For reducing the transistor and junction capacitances, it is known to use a negative substrate bias in NMOS technology, which is generated by a substrate bias generator on the integrated circuit (Halbleiter Elektronik, 14, H. Weiss, K. Horninger, "Integrierte MOS-Schaltungen", pp. 247-248). The latch-up effect resulting from positive semiconductor substrate biases is also described in this reference on page 111 through 112. The proposed solution to the latch-up problem presented in this reference is a modification of the doping profiles in the design of the semiconductor wells. Another proposed solution for suppressing the latch-up effect is presented in the publication of D. Takacs et al, "Static and Transient Latch-Up Hardness in n-Well CMOS With On-chip Substrate Bias Generator", IEDM 85, Technical Digest, pp. 504-508. This reference discloses a clamping circuit which prevents the latch-up effect in that the semiconductor substrate potential is limited to a value which is not sufficient for activating the parasitic bipolar transistors in the semiconductor substrate. To accomplish this, the clamping circuit shunts the high capacitive displacement currents to ground.
However, the prior art clamping circuit does not fundamentally exclude the possibility of a positive charging of the semiconductor substrate, rather the effects of latch-up are merely compensated in that, should a positive charging of the semiconductor substrate occur, a low impedance connection to ground is utilized to eliminate the positive charging.
The present invention overcomes these drawbacks in the prior art and in a circuit embodying the present invention the occurrences of latch-up effects are largely avoided.